Most modern digital systems spend much operating time with some or all major parts of the system idle, or nearly idle. Even fast typists rarely can provide input exceeding one character every 100 milliseconds. Although a cell phone or tablet must maintain a digital-radio listening watch while in “standby”, such phones spend most of their lives with display blanked, audio processing circuitry disabled, and camera shut down to conserve battery power. Older “CRT”-based televisions and monitors had vertical and horizontal retrace intervals, during which no video is displayed.
It is desirable to test digital systems periodically, because—as with all other manmade devices—they have been known to fail, both with permanent problems and with sensitivities to operating conditions such as high temperatures, radiation, and weak batteries.
While many digital systems perform at least some self-testing at “boot,” or power-up, time, one frustration of many users with many modern devices, including laptop computers, cell phones and similar devices, is the length of time required to “boot” the device.
Scan-chain testing is common in the art. In traditional scan testing, as illustrated in PRIOR ART FIG. 1, a functional unit 100 has a block of logic 102 that must be tested. Typically, all registers and state machines of the unit are separated from logic 102 into a scanable register 104. Scanable register 104 includes scanable “flip-flops” 106, each of which has two modes, a normal operation mode where an input to the flip-flop comes from logic 102, and a scan mode, where the input to the flip-flop comes from another flip-flop in the scanable register; each scanable flip-flop also provides an output into logic 102. In many systems where “D” flip-flops 108 are used, a 2:1 multiplexor 110 may serve to switch a flip-flop from a normal mode to the scan mode. The scanable flip-flops serve as a shift register, known as a scan chain, in scan mode, and as a normal register or set of flip-flops in normal mode.
Typically, a data input 112 is provided to the scan chain from a test mode interface circuit 120, and a data output 114 is provided from the scan chain to the test interface circuit 120.
A common clock 118 at each scanable flip-flop may be used for both modes in some systems, in some systems clock-switching circuitry is provided in test interface circuit 120, and in other systems two clocks are provided for each scanable flip-flop 106, with system clocks disabled during test operation. Typically, test interface circuit 120 brings data and clock signals in to the scan chain from an external tester 122 when test mode is activated, and provides data out to tester 122. Logic block 102 may receive additional inputs 124 from other subsystems or chips, and provide outputs 126 to those subsystems or chips; in many such systems any flip-flop or register associated with those inputs and outputs is typically implemented with scanable flip-flops 106 that are part of the scan chain. In larger systems, there may be more than one scan chain, where test interface circuit 120 includes logic to select an active scan chain from the scan chains provided.
Typically, scan testing is performed during a production test environment, where the system being tested performs no normal operations, and external tester 122 provides a sequence of “test vectors” to exercise logic block 102, the vectors typically include stimuli associated with inputs 124 as well as data for initializing each scanable flip-flop 106 of the scan chain to a desired state. The tester loads each vector into the scan chain and onto inputs 124, switches the scan chain to normal mode for one clock cycle to load outputs of logic 102 into the flip-flops of the scan chain, then switches the scan chain back to scan mode and sequentially reads out data from the scan chain, comparing data read from the scan chain to an expected value. Similarly, outputs 126 are compared to expected values during the clock cycle of normal mode.
Typically, scan testing is not performed during system operation, not even at boot time.